Change detector system

ABSTRACT

This disclosure deals with a system for detecting a change in a parameter represented by an analog signal. Integrating means receives the signal during a first time period and again during a second time period. The two time periods are preferably equal in duration and are adjoining. The results of the integration during the first period is compared with that of the second period. When the two time periods are equal, the results will be equal if the parameter has not changed during the two periods. If the results are different, a change in the parameter is indicated.

1 fr [191 [111 @fifiifid? Whitney et al. May 22, 1973 [54] CHANGEDETECTOR SYSTEM OTHER PUBLICATIONS [7 Inventors: J y; Peter Sorensen,Taylor, Analog-To-Digital Converter, IBM Tech. both of Fort Wayne, Ind.Disc. Bull., Vol. 3, No. 10, March 1961, pgs. 128-129 ['73] Ass1gnee:lll l'fgnklm Electric Co., llnc., Bluffton, Primary Examiner Malcolm AMorrison Assistant Examiner-James F. Gottman [22] Filed: Nov. 2, 1971 AItorney- Lowell C. Noyes and Donald J. Bratt [21] Appl. No.: 194,858[57] ABSTRACT This disclosure deals with a system for detecting a if 6235/92 change in a parameter represented by an I analog [58] Fill id.340 146 2' SignaL Integrating means receives the Signal during a 1 o 33 1 first time period and again during a second time 2 5/ 3 8 3 period.The two time periods are preferably equal in 24/7 30 22 duration and areadjoining. The results of the integration during the first period iscompared with that of [56] References cued the second period. When thetwo time periods are UNITED STATES PATENTS equal, the results will beequal if the parameter has not changed during the two periods. If theresults are 3,624,649 1 H1971 Ranieri ..235/92 EV X different, a changein the parameter is indicated, 3,548,183 12/1970 Jouve ....235/92 EV X3,582,882 6/1971 Titcomb et al. ..340/146.2 7 Claims, 3 Drawing FiguresT R A N s D U C E R START lJ-L i't 1i 17 GATE 33 GATE IDOWN u DETECTORPATENTEBHAYZZIQH 3P735,34T

SHEEI 1 [IF 3 TIME fig TRANSDUCER START BASE 17 GATE 23 GATE GATE ./21

new GP UP-DOWN COUNTER fzz REMAINDER r20 DETECTOR PATEN TED 2 SHEET 2 BF3 1 CHANGE DETECTOR SYSTEM When measuring a quantity or parameterrepresented by a signal, it is usually desirable to take a measurementwhen the signal is unchanging, in order to obtain an accuratemeasurement of the parameter. In a weighing system, for example, it isnecessary to let the weight receiving pan settle after placing anarticle thereon before making a measurement, and a measurement shouldnot be made when vibrations disturb the pan. Photocell arrangements havebeen used to detect motion, but motion detectors of this character areinadequate where the measuring apparatus experiences little or nomotion.

It is therefore an object of the present invention to provide a changedetecting system which receives an analog signal representing aparameter to be measured. The system includes integrating means whichreceives the signal during two time periods. During each period thesignal is integrated, and at the end of the two periods the results ofthe two integrations are compared. Where the two periods have equal timedurations, the two integrations are equal if the parameter has notchanged during the two periods. Inequality indicates a change in theparameter during the two periods. The two periods are preferablyconsecutive in time and have equal time durations.

Other objects, features and advantages of the invention will be apparentfrom the following detailed description taken in conjunction with theaccompanying figures of the drawings, wherein:

FIG. 1 is a block diagram of a frequency change detecting circuitembodying the invention;

FIG. 2 is a schedule of waveforms illustrating the operation of theinvention; and

FIG. 3 is a drawing showing in detail a circuit incorporating theinvention.

The system shown in FIG. 1 includes a circuit 9 for generating on aconductor 10 a full time base signal 241 (FIG. 2) having a predeterminedtime duration, and for generating on another conductor 11 a half timebase signal 25 (FIG. 2) having a time duration which is onehalf that ofthe full signal in response to a start signal on an input 13. Thecopending US. application of P.F. Sorensen, Ser.'No. 194,986, filed Nov.2, 1971, discloses a circuit which may be used for this purpose.Briefly, that circuit includes a binary counter which receives a trainof pulses from a stable oscillator. The counter includes a series ofconnected flip-flops, each flip-flop in the series toggling the nextflip flop when its output goes from logic one, or high, to logic zero,or low. In addition to the counter flip-flops, a separate flip-flop isconnected to the first and to the last flipflops of the counter series,toggling of the first counter flip-flop setting the separate flip-flopand toggling of the last flip-flop of the counter series resetting theseparate flip-flop. The Q output of the separate flip-flop provides thefull time base signal on the conductor 10. The time duration of the fulltime base signal is determined both by the frequency of the stableoscillator and by the capacity of the binary counter. While theabove-mentioned application does not disclose means for providing aone-half time base signal, this may be accomplished simply by connectingthe conductor 11 to the Q output of the next from the last flip-flop ofthe counter series. This Q output shifts to logic one when thisflip-flop is set, which occurs when the counter counts to one-half ofits capacity. The Q outputs fall to 1090 zero on the last count, suchfailings terminating the signals on the conductors 10 and 11.

The circuit 9 is preferably connected by a conductor 14 to receive theoutput of a transducer 16 which is also discussed in the above-mentionedSorensen patent application. The transducer produces a symmetrical wavesuch as a sine wave, and includes means for converting the sine wave toa symmetrical square wave. As described in the above-mentioned Sorensenpatent application, the leading or rising edge of the signal 24 on theconductor 10 essentially coincides with the leading edge of a squarewave on the conductor 14. The transducer 16 may, for example be a devicewhich responds to a parameter being measured and produces a signalhaving a frequency representative of the parameter. Before making such ameasurement it is desirable to wait until the device has stabilized andthe frequency is steady. A circuit in accordance with the presentinvention provides an indication of whether or not the transducer hasstabilized and the frequency is unchangmg.

The system shown in FIG. 1 includes three gates 17, 21 and 23, and eachof the three gates is designed to be turned on when both of its inputsignals are high or at logic one. The conductor 10 is connected to oneinput of the gate 17, and the conductor 11 is connected to a secondinput of the gate 17 after being inverted by an inverter 18. During thefirst half of a full time base signal, the one-half time base signal islow and, due to the inverter 18, a high signal appears at the associatedinput to the gate 17. Both of the inputs of the gate 17 being highduring the first half of the time base period, the gate 17 is turned onand a high output signal appears at the output 19 of the gate 17, theoutput 19 being connected to an input of another gate 21. The gate 21has a second input which receives the square wave signal from thetransducer 16, and when a high signal appears at the output 19, theoutput of the gate 21 corresponds to the transducer 16 output. The gate21 output is connected to an input of an integrator. In the presentillustration, the gate 21 is connected to an up-count input of anup-down counter 22.

The conductor 11 is also connected to an input of the gate 23, and asecond input of the gate 23 is connected to receive the signal from thetransducer 16. Since the half time base signal is low during the firsthalf of the full time base signal, the gate .23 is turned off and blocksthe signal from the transducer 16.

Thus, during the first half of the time base signal, the square wavesignal from the transducer 16 passes through the gate 21 to the counter22 which is designed to count up the number of trailing or falling edgesof the square wave, occurring within the the first half of the full timebase signal. As described in the previously mentioned Sorensenapplication, counting accuracy is improved by initiating the time basein synchronism with the leading edge of a square wave and counting onthe trailing edges.

At the end of the first half of the full time base signal, the half timebase signal on the conductor 11 rises to logic one, causing the gate 23to be turned on and the gates 17 and 21 to be turned off. The signalfrom the transducer 16 then flows through the gate 23 to the down-countinput of the counter 22, and the counter 22 downcounts on the leading orrising edges of the square wave from the transducer 16. At the end ofthe time base periods, the signals on both conductors l and 11 fall tozero and both gates 21 and 23 are turned ofi.

FIG. 2 is a schedule of waveforms illustrating the operation of thecircuit shown in FIG. 1. The full time base signal on the conductor isrepresented by the reference numeral 24 and the half base time signal onthe conductor 11 is represented by the reference numeral 25, which isone-half the length of the full time base signal. The numeral 26represents a square wave produced by the transducer 16, the square wave26 having, in the present illustration, a constant frequency throughoutthe time duration of the full time base signal 24. The leading edge 24aof the signal 24 essentially coincides with the leading edge 26a of acycle of the square wave 26. The leading or rising edge 25a of the halftime base signal 25 occurs half way through the full time signal 24, andboth signals 24 and 25 terminate simultaneously.

With reference to the square wave 26, approximately I 1% cycles occurduring both the first half and the second half of the full period of thesignal 24. Counting the trailing or falling edges of the cyclesoccurring during the first half and the leading or rising edges of thecycles occurring during the second half shows that 10 falling edgesoccur during the first half and 10 rising edges occur during the secondhalf, thus indicating that the frequency of the square wave 26 has notchanged during the full time base signal 24.

If the rising edges of the square wave 26 had been counted during bothcounting periods, 1 1 counts would have been registered during the firstcounting period and 10 counts would have been registered during thesecond counting period. Such operation obviously would provide anerroneous indication since the frequency has remained constant duringboth counting periods.

The reference numeral 27 represents another square wave having afrequency slightly lower than the frequency of the square wave 26, butagain, the frequency of the square wave 27 does not vary during the timeduration of the signal 24. A total of approximately 8% cycles of thesquare wave 27 occur during each counting period or half of the fulltime base signal 24. Eight falling edges are counted during the firstperiod and eight rising edges are counted during the second period,indicating that no change in frequency has taken place. Again, it shouldbe noted that nine rising edges of the square wave 27 occur during thefirst period, and consequently an erroneous output would have beenprovided if rising edges had been counted in both periods.

At other frequencies, errors would be encountered if the falling edgeswere counted during both periods. Where the first counting period isinitiated in synchronism with the rising edge of a square wave, accuracyis improved by counting the falling edges during the first period andrising edges during the second period. The reference numeral 29indicates another square wave wherein the frequency during the firstperiod is lower than the frequency during the second period.Approximately 7 l/l6 cycles of the wave 29 occur during the first periodand approximately 10 7/16 cycles occur during the second period. Sevenfalling edges of the wave 29 are counted during the first period and 10rising edges are counted during the second period. The two counts are ofcourse different and a remainder detector 20 (FIG. 1) detects the countof three remaining in the counter 22. The remainder detector 20 may beconnected to receive the full time base signal 24 so that itinterrogates the up-down counter 22 at the end of the signal 24, and itmay provide an output signal to an indicator or to any circuit thatresponds to a frequency change or lack of such a change.

While the circuits shown in FIGS. 1 and 3 are shown and described asswitching in response to time base signals produced by a time basecircuit, a timer could be used in place of the time base circuit, suchtimer being connected to control the gates to route the square wavesignal to the two counter inputs during the two periods. FIG. 3illustrates in detail the construction and operation of a circuit whichoperates similarly to the circuit shown in FIG. 1 but which differssomewhat in respect to the gating arrangement. The full time base signal24 is received on a conductor 30, the half time base signal 25 isreceived on a conductor 31, and the square wave signal from thetransducer 16 is received on a conductor 32. The circuit includes aninverter 33 connected to receive the signal 24 on the conductor 30, anda NOR gate 34 which has an input 35 connected to the output of theinverter 33. The NOR gate 34 has a second input 37 which is connected toreceive the half time base signal 25 on the conductor 31. During thefirst half of the signal 24, the signal 24 is high or at logic one, anddue to the inverter 33, a logic zero appears at the input 35.Simultaneously, the half time base signal 25 is low or at logic zero anda low signal appears at the input 37. With both inputs of the gate 34low, a logic one signal appears at its output 38 which is inverted byanother inverter 39. Consequently, a logic zero appears at an input 41of another NOR gate 42 during the first half of the full time basesignal 24.

Further, during the first half of the full time base signal 24, thesquare wave from the transducer 16 passes through a series connection oftwo inverters 47 and 48 and through an RC pulse shaping networkincluding a capacitor 49 and a resistor 50. The junction between thelatter two components is connected to another input 52 of the NOR gate42, and the resistor 50 is connected to a conductor 86 which isconnected to a source of, for example, +3.6 VDC.

Due to the two inverters 47 and 48, the square wave from the transducer16 appears at the output of the inverter 48, and the RC network producesa negative or falling pulse coinciding with each falling edge of thesquare wave on the conductor 32. The input 52 of the gate 42 is normallyhigh and the input 41 is low during the first half of the time basesignal 24, and therefore the output 53 of the gate 42 is normally low. Anegative pulse on the input 52 momentarily turns the gate 42 on thusforming a positive pulse at the output 53. This positive pulse isinverted by an inverter 54 to form a negative pulse which is fed to thecount-up input 56 of an up-down counter 58. In the present illustration,the counter 58 comprises an eight bit counter including eight connectedflip-flops. Thus, the falling edges of the square wave cause the counter58 to count up during the first half of the full time base signal 24until, at the end of this first counting period, the half time basesignal 25 on the conductor 31 rises to logic one and turns ofi the gate34.

Simultaneously, the transition to logic one of the half time base signal25 causes a logic zero signal to appear at in input 61 of another NORgate 62, an inverter 63 being interposed between the conductor 31 andthe NOR gate 62. The square wave signal on the conductor 32 passesthrough another inverter 64 to another RC pulse shaping networkincluding a capacitor 66 and a resistor 67, and a negative pulse appearson an input 68 of the NOR gate 62 for each falling edge of the signalout of the inverter 64. The input is normally high due to a connectionbetween the resistor 67 and the conductor and since the other input 61is low during the second half of the full time base, the output 69 ofthe NOR gate 62 is normally at logic zero. The negative pulse appearingat the input causes the output 69 to rise momentarily to logic one, andthis momentary rise, or pulse, is inverted by another inverter 71,resulting in a negative pulse appearing on a down-count input 72 of thecounter 58 for each rising edge of the transducer square wave occur-ingduring the second counting period or half of the full time base signal.

At the end of the counting periods, the signals 24 and 25 on theconductors 30 and 31 fall to zero, resulting in the two gates 34 and 62being turned 011 and blocking the square wave from passing to eitherinput 56 or 72 of the counter 58.

As previously mentioned, at the beginning of a time base the rising edge24a of the signal 24 on the conductor 30 causes a logic zero signal toappear on a conductor 73 connected to the output of the inverter 33. Theconductor 73 is connected to a reset or clear input 74 of the counter 48through a series connection of four inverters 76 to 79 and an RC pulseshaping network including a capacitor 81 and a resistor 82. The risingedge 240 causes a negative pulse to appear at the input 74 to clear thecounter 58 at the beginning of a measuring cycle.

The counter 58 also includes a power input indicated generally by thereference numeral 83, a conductor 84 being connected between the powerinput and ground, and another conductor 85 being connected between theinput and a DC source of, for example, +13 volts. Another conductor 86is connected to, for example, +3.6 VDC.

As previously mentioned, the counter 58 comprises, in the presentinstance, an eight-bit up-down counter, and has eight output conductors91 through 98. The conductors 91 to 98 are respectively connected to theQ outputs of the l, the 2, the 4, the 8, the l6," the 32, the 64, andthe 128 flip-flops. A pulse on the clear input 74 sets the 2" flip-flopand resets the remaining flip-flops, and consequently the conductors 91and 93 through 98 are at logic zero and the conductor 92 is at logicone. Thus, the counter 58 is preset to a count of 2. Such a preset isnot necessary but is desirable in some instances because, with thegating arrangement to be described, a difference in counts between thetwo counting periods of zero plus or minus one indicates no change infrequency.

The outputs 91 to 98 are connected to an interrogating circuit whichindicates, at the end of the two counting periods, whether anydifference in the two counts is tolerable or excessive. The fourconductors 95 through 98 are connected to four inputs of a NOR gate 101,and when all of the conductors 95 through 98 are at logic zero, the gate101 is turned on and the output 102 of the gate 101 is high. Theconductors 91 and 92 are connected to two inputs of a NOR gate 103 whichhas its output 104 connected to input of another NOR gate 106. Theconductors 93 and 94 are connected to two additional inputs of the NORgate 1, and the output 107 of the NOR gate 1 is connected to the output102 of the gate 101 and to an input 108 of still another NOR gate 109.The gate 109 has a second input 111 connected to receive the full timebase signal 24 appearing on the conductor through the inverter 33,another inverter 112 and an RC pulse shaping network including acapacitor 113 and a resistor 114. The falling edge of the full time basesignal, at the end of the second counting period, causes a negativepulse to appear at the input 111 of the gate 109.

At the end of the counting period, if the frequency has not changedduring the up count and the down count, the conductors 91 and 93 through98 will all be at logic zero, and the conductor 92 will be at logic one.The output 102 of the gate 101 will be at logic one, but since theconductor 92 is at logic one, logic zero appears on the output 1 of thegate 103. Thus, the three inputs to the NOR gate 106 will be at logiczero and therefore the output 107 will be at logic one. When thenegative interrogating pulse appears at the input 111, the logic onesignal at the input 108 results in a logic zero signal at the output ofthe NOR gate 109, this latter signal indicating that the frequencyeither has not changed during the two counting periods or, if it haschanged, the difierence in counts is within tolerable limits.

If the counter 58 counts up one more cycle during the first half of thefull time base signal than down during the second half, the remainder inthe counter 58 will be three because of the preset number two and thefrequency difference of one. Thus, the conductors 91 and 92 will both beat logic one and the output 104 of the gate 103 will again be at logiczero, similar to the preceding example where the counter was returned toits initial state. Thus, the system indicates no frequency change eventhough there is one cycle difference in the two counts.

If the counter 58 counts up one cycle during the first half less thandown during the second half, the remainder in the counter 58 will beone. The conductor 91 will be high and the conductor 92 will be low andagain the gate 103 output will be low. Consequently, the system againindicates no frequency change even though there is a frequencydifference of one.

If the counter 58 counts two more cycles in the first period than arecounted in the second period, the residual count in the counter 58 willbe four. The conductors 91 and 92 will be low and the conductor 93 willbe high. The high signal on the conductor 93 causes the gate 106 to below, which causes the input 108 to be logic zero. The negativeinterrogating pulse appearing on the input111 of the gate 109 results ina positive pulse at the output 120, indicating that an excessivefrequency difl'erence has occurred.

It will be apparent that, when there is a remainder count of one, two orthree, one or both of the outputs 91 and 92 will be high, the output 104will be low, the output 107 will be high and the output 120 will remainlow when the interrogating pulse appears on the input 111. Ifthe countremaining at the end of the two counting periods is two plus or minustwo or more, a positive pulse will appear on the output 120 in responseto an interrogating pulse.

In some instances it may be desirable to detect a difference of a singlecount between the two periods, or to tolerate a count difierence of morethan plus or minus one. The arrangement of the counter 58 and the gatesconnected to the counter outputs may be fashioned to obtain the desiredresult.

While in the present illustration all of the flip-flops of the counter58 are interrogated at the end of the second period, an arrangement maybe used where only the lowest two or three digits are interrogated, withlittle chance of error. While an up-down binary counter has beenillustrated and described, it should be apparent that other types ofcounters, such as a decade counter, could be used. Further, instead ofan up-down counter, two separate counters, one for each counting period,could be used in conjunction with means for comparing the counts of thetwo counters. In accordance with the present invention, any type ofintegrating means, which in the present illustration is a counter, maybe provided to receive the analog signal (the variable frequency signalin the present illustration) and to integrate the signal during eachperiod.

While two counting periods of equal time duration have been described,it would of course be possible to have two periods of unequal durationand fashion the counter and interrogating circuit to tolerate acorresponding difierence in counts.

It should be apparent that the circuits disclosed herein may be composedof either electric or fluidic circuit components.

While the assignment of logic levels described herein for illustrationpurposes is the case where logic one is high and logic zero is low, itshould be realized that an opposite assignment could be made where logicone is low and logic zero is high. In a system of the latter character,the NOR gates disclosed herein would be replaced by NAND components andthe OR gates would be replaced by AND components.

The invention described herein is highly advantageous because it readilypermits a determination of whether a parameter, represented by an analogsignal, is steady or is changing, and because the circuit may bearranged to tolerate a change within acceptable limits.

We claim:

1. A detecting circuit for detecting a change in the frequency of avariable frequency substantially symmetrical signal having a leadingedge and a trailing edge in each cycle, comprising counting means, meansconnecting said signal to said counting means during one 8 period andduring another period, said counting means making a count of saidleading edges during said one period and another count of said trailingedges during said other period, and detecting means connected to saidcounting means and responsive to a difference between said two counts.

2. A circuit as in claim 1, wherein said one period is initiatedessentially in synchronism with the leading edge of a cycle.

3. A circuit as in claim 1, wherein said connecting means comprises timebase signal generating means and gating means connected to receive atleast one time base signal from said generating means for connectingsaid variable frequency signal to said counting means during saidperiods.

4. A circuit as in claim 3, wherein said counting means is an up-downcounter, and said time base signal generating means provides two timebase signals, one time base signal having twice the time duration as theother time base signal, said connecting means responding to said twotime base signals to connect said variable frequency signal to causesaid counter to count up during said one period and to count down duringsaid other period.

5. A circuit as in claim 1, wherein said up-down counter is preset to acount of two prior to said periods, and said difference responsive meansindicates when the count at the end of said other period is greater thantwo plus or minus one.

6. A circuit as in claim 3, wherein said time base signal is connectedto clear said counting means at the beginning of said one period, and isconnected to actuate said detecting means at the end of said otherperiod.

7. A circuit for detecting a change in a symmetrical cyclically varyingsignal which in each cycle includes a first point and a second pointthat is displaced one-half cycle from said first point, comprisingintegrating means, means connected to said integrating means and formingfirst and second time periods, said integrating means being adapted toreceive said signal during said first and second periods and form afirst integration of said first points and a second integration of saidsecond points, and detecting means connected to said integrating meansand responsive to a difference between said first and secondintegrations at the end of said periods. l l

1. A detecting circuit for detecting a change in the frequency of avariable frequency substantially symmetrical signal having a leadingedge and a trailing edge in each cycle, comprising counting means, meansconnecting said signal to said counting means during one period andduring another period, said counting means making a count of saidleading edges during said one period and another count of said trailingedges during said other period, and detecting means connected to saidcounting means and responsive to a difference between said two counts.2. A circuit as in claim 1, wherein said one period is initiatedessentially in synchronism with the leading edge of a cycle.
 3. Acircuit as in claim 1, wherein said connecting means comprises time basesignal generating means and gating means connected to receive at leastone time base signal from said generating means for connecting saidvariable frequency signal to said counting means during said periods. 4.A circuit as in claim 3, wherein said counting means is an up-downcounter, and said time base signal generating means provides two timebase signals, one time base signal having twice the time duration as theother time base signal, said connecting means responding to said twotime base signals to connect said variable frequency signal to causesaid counter to count up during said one period and to count down duringsaid other period.
 5. A circuit as in claim 1, wherein said up-downcounter is preset to a count of two prior to said periods, and saiddifference responsive means indicates when the count at the end of saidother period is greater than two plus or minus one.
 6. A circuit as inclaim 3, wherein said time base signal is connected to clear saidcounting means at the beginning of said one period, and is connected toactuate said detecting means at the end of said other period.
 7. Acircuit for detecting a change in a symmetrical cyclically varyingsignal which in each cycle includes a first point and a second pointthat is displaced one-half cycle from said first point, comprisingintegrating means, means connected to said integrating means and formingfirst and second time periods, said integrating means being adapted toreceive said signal during said first and second periods and form afirst integration of said first points and a second integration of saidsecond points, and detecting means connected to said integrating meansand responsive to a difference between said first and secondintegrations at the end of said periods.